The present invention relates to a protection circuit for suppressing destruction of an internal circuit by fluctuations in high voltage due to electrostatic discharge (ESD) for an input terminal and a power source terminal in a semiconductor integrated circuit.
Japanese Patent Laid-open No. 2004-14929 (FIG. 1, paragraph 0060) discloses a protection circuit against the ESD having a configuration including a resistive element and a capacitive element connected in series between a power source line and a ground line, a CMOS inverter whose input is connected between the resistive element and the capacitive element, and an n-channel type clamp MOS transistor whose gate electrode receives an output of the CMOS inverter and whose drain electrode and source electrode are connected to the power source line and the ground line. In a normal state, an output of the CMOS inverter is set to the low level, and the clamp MOS transistor is set to an off state. When fluctuations in high voltage caused by the ESD occur in the power source line, a level change at the connection point between the resistive element and the capacitive element is delayed according to the time constant, rise of the input level of the CMOS inverter is delayed from rise in the level on the operation power source side of the CMOS inverter, thereby setting an output of the CMOS inverter to the high level for a predetermined period. Only in the period, the clamp MOS transistor is set to the on state, and high voltage of the power source line is allowed to escape to the ground line.